There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon pixel detectors.Others,such as time measurement detec-tors,require a high time resolution based on the time-to-digital readout architecture.A phase-locked loop(PLL)is an essential and broadly used circuit in these applications.This study presents an application-specific integrated cir-cuit of a low-jitter,low-power LC-tank that is PLL fabri-cated using 55-nm CMOS technology.It includes a 3rd-order frequency synthesis loop with a programmable bandwidth,a divide-by-2 pre-scaler,standard low-voltage differential signaling interfaces,and a current mode logic(CML)driver for clock transmissions.All the d-flip-flop dividers and phase-frequency detectors are protected from single-event upsets using the triple modular redundancy technique.The proposed VCO uses low-pass filters to suppress the noise from bias circuits.The tested LC-PLL covers a frequency locking range between 4.74 GHz and 5.92 GHz with two sub-bands.The jitter measurements of the frequency-halved clock(2.56 GHz)are less than 460 fs and 0.8 ps for the random and deterministic jitters,respectively,and a total of 7.5 ps peak-to-peak with a bit error rate of 10-12.The random and total jitter values for frequencies of 426 MHz and 20 MHz are less than 1.8 ps and 65 ps,respectively.The LC-PLL consumed 27 mW for the core and 73.8 mW in total.The measured results nearly coincided with the simulations and validated the analyses and tests.

Xiao-Ting Li;Wei Wei;Ying Zhang;Xiong-Bo Yan;Xiao-Shan Jiang;Ping Yang

State Key Laboratory of Particle Detection and Electronics,Experimental Physics Department,Institute of High Energy Physics,Chinese Academy of Sciences,19B Yuquan Road,Beijing 100049,China;School of Physical Sciences,University of Chinese Academy of Sciences,19A Yuquan Road,Beijing 100049,China;PLAC,Key Laboratory of Quark and Lepton Physics(MOE),Central China Normal University,152 Luoyu Road,Wuhan 430079,China

核技术（英文版）

[1]Xiao-Ting Li;Wei Wei;Ying Zhang;Xiong-Bo Yan;Xiao-Shan Jiang;Ping Yang-.A 5.12-GHz LC-based phase-locked loop for silicon pixel readouts of high-energy physics)[J].核技术（英文版）,2022(07):14-24

readouts,scaler,dividers,upsets,jitters

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